SEU-induced persistent error propagation in FPGAs
نویسندگان
چکیده
منابع مشابه
Robust SEU Mitigation With Stratix III FPGAs
The benefits of FPGAs over ASICs become ever more compelling as rapid-process technology scaling and innovation provide ever-greater speed, density, and power improvements. However, along with technology scaling come other effects that previously could be ignored. One of the accompanying effects is increased susceptibility to soft errors caused by single event upsets (SEUs). Although through ca...
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Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip (SoC) implementations. The case studies include embedded hard core and soft core processors which manipulate configuration memory bits to emulate physical and transient faults in the FPGA core including shorts and op...
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Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability, high-reliability, and safety-critical systems. However, along with technology scaling come other effects such as increased susceptibility to soft errors that previously could be ignored. These soft error...
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SRAM-based reconfigurable programmable logic is widely used in commercial applications and occasionally used in space flight applications because of its susceptibility to singleevent upset (SEU). Upset detection and mitigation schemes have been tested on the Xilinx Virtex II X-2V1000 in heavy-ion and proton irradiation to control the accumulation of SEUs and to mitigate their effects on the int...
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ژورنال
عنوان ژورنال: IEEE Transactions on Nuclear Science
سال: 2005
ISSN: 0018-9499
DOI: 10.1109/tns.2005.860674